SARC Power Estimation Methodology

In modern CMOS technologies, power consumption is becoming a significant challenge for the integrated circuits industry. Accurate estimation of power dissipation is very important during micro-architectural design of every computational structure. This work presents the methodology we intent to use in future investigations regarding power consumption of the SARC architecture. SARC project is targeting next generation scalable computer architectures where multiple cores will be responsible for the performance gains. Proposing new approaches to reduce power consumption and scale for power and performance in the architectural development is one of the main challenges of this project. Therefore, adequate methodology to estimate it is needed. In this paper, we introduce the tools (i.e., Unisim simulator and Cacti 4.0) and the proposed methodology to investigate the problem of power consumption in such architecture. Keywords—Power Estimation, Low Power Design, Power Management, Unisim Simulator, Cacti 4.0